The present invention generally relates to semiconductor devices and more particularly to a semiconductor device having a ball grid array and a fabrication process thereof, including a transportation tray used in the fabrication process of the semiconductor device. Further, the present invention relates to the fabrication process of a semiconductor substrate used for such a semiconductor device.
With ever-increasing demand of size reduction of electronic apparatuses, efforts are being made for decreasing the size and increasing the integration density of semiconductor devices. In relation to this, there is a proposal of a so-called chip-size package structure in which the overall size of the semiconductor device is made close to the size of the semiconductor chip therein.
In order to achieve such a real chip-size package structure, as well as for improving the efficiency of production of the semiconductor devices having such a package structure, there is a proposal of a wafer-level packaging process in which a substrate carrying a plurality of semiconductor devices thereon is subjected to a packaging process in the state that the semiconductor devices are still on the semiconductor substrate, followed by a dicing process to form individual semiconductor chips corresponding to the semiconductor devices.
FIG. 1 shows an example of a semiconductor device 10A fabricated according to a conventional wafer-level packaging process.
Referring to FIG. 1, the semiconductor device 10A generally includes a semiconductor chip 1A, a resin package layer 2 and a plurality of bump electrodes 3.
More specifically, the semiconductor device 10A carries the resin package layer 2 on the surface of the semiconductor chip 1A on which active devices (monolithic electronic circuits) and the bump electrodes 3 are formed. The substrate is then diced into individual semiconductor devices 10A. The semiconductor device 10A thus formed has a size substantially identical to the size of the semiconductor chip 1A.
FIG. 2 shows the construction of a conventional transportation tray 5 used for transporting the semiconductor device 10A of FIG. 1.
Referring to FIG. 2, the transportation tray 5 includes a tray main-body 6 accommodating therein the semiconductor device 10A, and a cap 7 is provided on the train main-body 6 so as to cover the opening of the tray main-body 6. The tray main-body 6 includes a bottom overhang part 8 wherein the bottom overhang part 8 supports the semiconductor device 10A by engaging the resin package layer 2 on the semiconductor chip 1A. The overhang part 8 defines an opening for accommodating the bump electrodes 3 in the state that the semiconductor device 10A is held inside the transportation tray 5.
FIG. 3 shows another conventional semiconductor device 10B fabricated according to a conventional wafer-level packaging process.
Referring to FIG. 3, the semiconductor device 10B generally includes, in addition to the semiconductor chip 1A described in FIG. 1, bump electrodes 4 formed on the semiconductor chip 1A and a circuit substrate 9 provided on the bump electrodes 4 in electrical as well as mechanical connection with the bump electrodes 4, wherein an under-fill resin layer 11 is formed so as to fill the gap between the semiconductor chip 1A and the circuit substrate 9. It should be noted that the bump electrodes 3 forming a ball grid array are formed on the bottom surface of the circuit substrate 9. By using the circuit substrate 9, which carries wiring patterns thereon, a dense array of the bump electrodes 3 becomes possible.
FIG. 4 shows a further conventional semiconductor device 10C fabricated according to a conventional wafer-level packaging process.
Referring to FIG. 4, the semiconductor device 10C has a construction generally identical with the construction of the semiconductor device 10B except that a thin semiconductor chip 1B is used. The semiconductor chip 1B having such a reduced thickness may be formed by grinding the rear surface of the semiconductor chip 1A.
FIGS. 5A–5D are diagrams showing an example of the fabrication process of a conventional semiconductor device.
In recent process of fabricating semiconductor devices, there is a tendency to increase the size of the semiconductor substrate so as to maximize the efficiency of production of the semiconductor devices. In order to obtain such a large-diameter semiconductor substrate, it is necessary to slice a large-diameter semiconductor crystal ingot by a wire saw machine and process the both surfaces of the large-diameter semiconductor wafer thus obtained.
FIG. 5A shows a semiconductor substrate 12A immediately after the sawing process. As can be seen in FIG. 5A, the both surfaces of the semiconductor substrate 12A form a rough surface, and thus, a smoothing process is essential in order that the semiconductor substrate 12A can be used for the substrate of a semiconductor device.
Thus, in the step of FIG. 5B, a hypothetical target surface state 13 is set for the semiconductor substrate 12A, and the rear surface (top surface in the example of FIG. 5B) of the semiconductor substrate 12A is processed in the step of FIG. 5C while using the top surface as a reference surface, such that the state of the rear surface reaches the target surface state 13. Further, the front surface (bottom surface in the example of FIG. 5B) is processed similarly in the step of FIG. 5D. The semiconductor devices 10A, 10B or 10C are formed on such a semiconductor substrate 12A in a row and column formation.
As noted already, the semiconductor device 10A has an advantageous feature in that the desired high-density mounting is possible on a circuit substrate of an electronic apparatus. On the other hand, it should be noted that the semiconductor device 10A has a composite structure 10 in which the semiconductor chip 1A carries a resin layer 2 on the side where the electrode bumps 3 are formed. As the resin layer 2 has a property substantially different from the property of the semiconductor chip 1A or the semiconductor substrate 12C, and in view of the fact that the semiconductor chip 1A, including the resin layer 2 thereon, has a rectangular shape defined by sharply defined edges and corners, there arises a problem, when sawing the semiconductor substrate 12C into the semiconductor chips 1A or when handling the semiconductor device, in that a crack may be formed at the boundary between the semiconductor substrate 12C and the resin layer 2. Alternatively, the semiconductor chip 1A or the resin layer 2 itself may be cracked. The same problem occurs not only in the semiconductor chip 1A but also in the semiconductor chip 1B or 1C.
Further, even in such a case in which the problem of cracking is avoided, the semiconductor device 10A, 10B or 10C is still vulnerable to damages particularly at the boundary between the semiconductor chip 1A and the resin layer 2, and a careful handling is needed in a suitable protective environment.
Further, the use of the transportation tray 5 of FIG.2 in combination with the semiconductor device 10A, 10B or 10C may cause the problem of rattling of the semiconductor device 10A inside the tray main-body 6, while such a rattling is not only disadvantageous in view of poor reliability of transportation but also in view of unreliable contact with a test bed used when testing the semiconductor device 10A in the state that the semiconductor device 10A is held by the transportation tray 5. Further, the rattling of the semiconductor device 10A in the transportation tray 5 may cause a damage in the solder bumps 3 as a result of collision with the bottom overhang part 8 of the transportation tray 5.
In the case of the semiconductor device 10C in which the thickness of the semiconductor chip 1B is reduced, the semiconductor device is extremely fragile and handling of the substrate has to be conducted with an utmost care. This problem becomes particularly serious when a large size substrate is used for increasing the efficiency of production of the semiconductor devices.
Further, the process of forming the semiconductor substrate 12A shown in FIGS. 5A–5D has a drawback in that the substrate 12A tends to show an undulation formed at the time of sawing the semiconductor crystal ingot by a wire saw machine. Such an undulation is difficult to be removed by a mere grinding process conducted by using the surface 13 as a reference surface.